Wafer Processing Systems for Advanced Packaging

Wafer Processing Systems for Advanced Packaging

SPTS offers a range of plasma etch and deposition process technologies for advanced packaging schemes - from High Density Fan-Out Wafer-Level Packaging (FOWLP) to the most advanced 3D packages where two or more die, potentially for different functions, are stacked and connected in the vertical direction with through-silicon vias (TSV) filled with metal. Leveraging decades of expertise in silicon etching, SPTS also offers the most advanced plasma dicing solutions for dicing before grind (DBG) or dicing after grind (DAG) of wafers up to 300mm in diameter. SPTS’s production-proven processes and precise process control allow chip manufacturers to lower production costs and improve reliability, performance and multi-function integration.

Omega® Plasma Etch

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Omega® Plasma Etch

Plasma Etch Systems for Silicon

The SPTS Omega® plasma etch systems include the Rapier™ range of process modules for high rate silicon etching in advanced packaging applications. Rapier™ etch modules are used to create vertical or tapered, high aspect ratio via holes or slots through silicon wafers or interposers for 2.5D/3D-IC packaging applications, and for blanket via reveal etching to expose the Cu-filled vias from the backside of the wafer. The Rapier™ XE process module combines recipe tuneable uniformity with an etch rate that is typically 2-4 times faster than competing systems for a blanket silicon etch. The same process can be used for extreme wafer thinning down to 5µm or even 0.5µm through the incorporation of an etch stop layer. SPTS also offers unique, patent-protected end-point solutions for TSV etching, via reveal and extreme thinning processes which enable optimal throughput and yields in high volume production.

Applications
TSV etch, blanket silicon etch for via reveal or wafer thinning
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Mosaic Plasma Dicing

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Mosaic Plasma Dicing

Plasma Dicing Systems

The SPTS Mosaic™ plasma dicing systems from SPTS offer an alternative to mechanical saw or laser technologies, for singulation of die from a silicon wafer (up to 300mm, on frames). This solution offers a low damage, dry chemical process which increases die strength and avoids particulate contamination. These benefits are especially important when the wafers are thin or contain fragile low k films and for die to wafer bonding. Being a parallel process, plasma dicing offers significant throughput, yield and cost advantages when dicing small die and/or thin wafers. Narrower dicing lanes allow for more die per wafer, and no restrictions on die shape allows for optimized wafer layouts.

Applications
Die singulation, particularly for very small die, thin wafers or die to wafer bonding
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Sigma® PVD

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Sigma® PVD

Physical Vapor Deposition Systems for Metal Deposition

The SPTS Sigma® PVD systems are used to deposit metals such as Au, Al, Ti, TiW and Cu, on Si or mold wafers. The adoption of organic passivation and new substrate materials for advanced packaging technologies present technical challenges for under bump metallization (UBM) and redistribution layers (RDL). Using novel degas and pre-clean technology, the Sigma® PVD systems produce consistently low Rc values while delivering a 2 times throughput advantage over other PVD systems. In 2.5D and 3D-IC applications, SPTS’s Advanced Hi-Fill® Ionized PVD source delivers world-class Cu barrier/seed coverage in high aspect ratio TSVs.

Applications
Under-bump metal (UBM) and re-distribution layers (RDL) on Si and FO-WLP mold wafers, TSV barrier/ seed layers
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Delta PECVD

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Delta PECVD

Plasma Enhanced Chemical Vapor Deposition Systems

For advanced packaging applications, the SPTS Delta™ PECVD system offers low temperature deposition processes compatible with 300mm bonded substrates and mold. Delta™ PECVD produces high quality, production qualified SiO and SiN films at deposition temperatures as low as 110°C. SiN – SiO stacks can be deposited in the same PECVD chamber with high reliability electrical performance and stability over time. Film and stack stress can be tuned across a wide range and optimized chamber hardware enables the lowest within-wafer stress range over competing PECVD systems. Where required, single-wafer and multi-wafer degas options are available to heat outgassing substrates and improve deposited film quality. Optimized SiO, TEOS SiO and other advanced dielectric films are available for fusion bonding applications.

Applications
Via-last TSV liner, via reveal passivation, stress-compensation layers for thinned wafers, dielectrics for fusion bond
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