The WaferSight™ PWG2 (Patterned Wafer Geometry) metrology system enables patterned wafer geometry control for the 1Xnm design nodes. Built on the production-proven WaferSight platform, it is a single-tool solution for measuring stress-induced wafer shape changes, wafer shape-induced overlay, wafer thickness variations and wafer front- and backside topography. With significantly increased productivity compared to its predecessor, the WaferSight PWG2 delivers increased wafer sampling in production for in-line monitoring of processes such as thin films, etch, anneal and other modules – enabling faster yield ramp, overlay control, and lithography focus window control.
WaferSight PWG2 is a key product in KLA-Tencor’s 5D™ Patterning Control Solution™, which drives optimal patterning through the characterization and monitoring of fab-wide processes. Through close integration with KLA-Tencor’s 5D Analyzer® data analysis system, WaferSight PWG2 data is utilized in feedback and feed forward modes. The WaferSight PWG2’s comprehensive wafer stress and shape uniformity data can be fed back to fab processes, helping chipmakers identify and fix process variations that can cause patterning and yield issues. This same data can also be fed forward to the lithography module, allowing engineers to understand whether overlay errors caused by wafer shape variations can be compensated for by using current scanner controls. Because 5D Analyzer can also calculate overlay issues that are not related to wafer shape, engineers can use this data analysis system to combine shape and non-shape overlay corrections into a single scanner correction file for improved litho performance.
WaferSight PWG Measurement Capability
The WaferSight PWG2’s industry-unique vertical wafer hold enables full measurement of both the wafer’s front side and backside without gravitational distortion effects. This allows calculation and/or detection of:
- Wafer shape variation
- In-plane displacement
- Stress-induced local curvature
- Wafer thickness and flatness variation
- Front and back surface Nanotopography (NT)
- Wafer edge roll-off (ERO)
Process Monitoring: The WaferSight PWG2 produces comprehensive wafer stress and shape uniformity data, enabling process tool monitoring and matching for film deposition, anneal, etch and other process modules. The WaferSight PWG2’s proven metrics help reduce process development time through faster root cause determination. In addition, the WaferSight PWG2’s productivity improvements promote increased wafer sampling in production, helping chipmakers identify and fix process-induced wafer stress variations that can result in significantly reduced process windows. In high volume manufacturing, the WaferSight PWG2 helps optimize and monitor a wide range of fab processes, and supports fab applications such as:
- Process optimization and in-line monitoring to control wafer shape variations for film deposition and RTP processes
- Chamber matching of film deposition tools such as CVD processes
- In-line monitoring of local stresses within a wafer arising from film deposition processes for vertically integrated devices, such as 3D NAND flash
- In-line monitoring of CMP processes for wafer flatness and/or NT, thereby reducing scanner defocus at downstream litho operations
Lithography Control: The WaferSight PWG2’s wafer shape data from pre-litho fab processes can be fed forward to the scanner to address overlay errors due to wafer stress – a particular concern for 3D NAND devices, which utilize thick film stacks that can distort wafers. In addition, the WaferSight PWG2 generates wafer flatness and topography metrics that can improve prediction and control of scanner focus. With rapidly shrinking overlay and focus process windows for 1Xnm and below design nodes, the WaferSight PWG2 can play a key role in expanding litho process windows through:
- Identification of sources of higher order shape component of lithography overlay residuals otherwise not correctable by scanner. WaferSight PWG2 uses wafer backside measurements for such calculations, thus eliminating pattern effects from the wafer’s front side
- Qualifying scanner chuck flatness variation
- In-line monitoring of non-litho processes for wafer flatness and/or NT, thereby reducing scanner defocus at downstream litho operations
- Qualification and in-line monitoring of ERO characteristics impacting scanner depth of focus (DOF) budget at the wafer’s near-edge region
WaferSight PWG: First-generation patterned wafer geometry measurement system, supporting fab process monitoring and litho control applications for the sub-20nm design nodes.
To find out more about WaferSight for unpatterned wafer applications, please see the WaferSight wafer manufacturing segment page.