Wafer Geometry and Nanotopography Scanner Systems
WaferSight PWG



Product Description 

The WaferSightTM PWG (Patterned Wafer Geometry) metrology system enables 1X nm design rule wafer geometry control for both patterned and unpatterned wafers. Built on the production-proven WaferSight platform, it is a single-tool solution for stress-induced wafer shape changes, shape-induced overlay, wafer thickness variation and front- and back-side topography. WaferSight PWG enables faster process ramp, overlay control, litho focus window control and in-line process monitoring for processes such as thin films, etch, CMP and RTP.

WaferSight PWG is part of KLA-Tencor’s 5DTM Patterning Control solution, along with the LMS IPRO6 reticle pattern placement metrology system, ArcherTM overlay metrology system, and K-T Analyzer® data analysis system. WaferSight PWG data can be imported into K-T Analyzer. This allows lithography engineers to understand whether shape-induced overlay can be compensated for by using current scanner controls. Because K-T Analyzer can also calculate non-shape related overlay issues, engineers can use this software to combine shape and non-shape overlay into a single scanner correction file for litho exposure.

Process induced-shape changes cause in-plane displacement within the wafer when it is chucked on the litho scanner. In-plane displacement - when not corrected for - can cause excessive overlay residuals. Besides changing wafer shape, local stresses resulting from film deposition or thermal processes can also cause local topography changes impacting overlay and focus. Local wafer thickness variations can cause scanner defocus during wafer edge exposure. Deviations in a wafer’s edge roll-off (ERO) create defocus defects near the wafer edge, and reduce the ability to print yielding edge die. Nanotopography (NT) influences the uniformity of material removal during CMP. The WaferSight PWG (Patterned Wafer Geometry) helps to identify these issues, helping chipmakers drive improvements in their processes.

WaferSight PWG (Patterned Wafer Geometry) measurement capability

A vertical wafer hold enables full wafer measurement of both the front- and back-side without gravitational distortion effects and calculate/detect:

  • Wafer shape variation
  • In-plane displacement
  • Stress-induced local curvature
  • Wafer thickness and flatness variation during wafer edge exposure
  • Front and back surface Nanotopography (NT)
  • Wafer edge roll-off (ERO)
  • Sliplines

WaferSight PWG (Patterned Wafer Geometry) Applications

WaferSight PWG can be used to qualify, monitor and control processes in both feedback and feedforward modes for a number of fab applications. Proven metrics help reduce process development time through faster root cause determination. With rapidly shrinking overlay and focus process windows for 2X nm and below design nodes, WaferSight PWG can play a key role in expanding litho process windows by:

  • Identification of sources of higher order shape component of litho overlay residuals otherwise not correctable by scanner. WaferSight PWG uses wafer backside measurements for such calculations thus eliminating pattern effects from the wafer frontside
  • Process optimization and in-line monitoring to control wafer shape change for film deposition and RTP processes
  • Chamber matching of film deposition tools such as CVD processes
  • In-line monitoring of local stresses within a wafer arising from film deposition processes for vertically integrated devices
  • Optimization of litho masks/reticles based on intra-field overlay and stress variations
  • Qualifying scanner chuck flatness variation
  • In-line monitoring of CMP processes for wafer flatness and or NT reducing scanner defocus at downstream litho operations
  • Qualification and in-line monitoring of ERO characteristics of bevel etch processes impacting scanner DOF budget at wafer edge

To find out more about WaferSight for unpatterned wafer applications, please see the WaferSight wafer segment page

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