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PROLITH X3.1 virtual lithography tool uses advanced models to quickly and accurately predict how pattern will print on the wafer for 2Xnm and below design nodes. This virtual lithography tool is used by advanced IC manufacturers, stepper companies, track companies, mask manufacturers, material providers and research consortia to cost-effectively evaluate EUV, double patterning and other advanced lithography technologies. As a critically important tool for leading-edge lithography, PROLITH X3.1 helps lithographers expand their areas of research while significantly reducing the time required to identify workable lithography solutions.

The PROLITH X3.1 virtual lithography tool includes several features for investigating different lithography technologies and issues, including:

• The first commercially available stochastic resist model that takes into account the quantum nature of light and the discrete reactant molecules in the resist to:
  
  • Accurately and quickly predict line edge roughness (LER), and explore potential solutions for minimizing LER;
  • Investigate pattern printing repeatability, and study the impact on yield;
  • Study line and contact hole CD uniformity;
  • Determine the usable process window;
  • Examine how different resist reactant loading levels affect printing (e.g. process windows, CD control, defect levels), allowing material companies to explore resist formulations at significantly reduced cost.
• The first commercially available, fast model that simulates the photoelectron effect to accurately determine the outcome of EUV lithography.
• Intuitive wafer topography set-up and improved wafer topography models that allow for fast, easy evaluation of double and single patterning non-planar lithography stacks.
• Database of over 60, high-accuracy, expertly calibrated resist models, available for immediate use.
• Intuitive interface that runs on a 32-bit PC, providing fast, accurate lithography models without the need for computer upgrades or supercomputers.
• Available as an upgrade to the industry-leading PROLITH platform, providing extendibility to researchers’ existing capital investments.

Applications
Advanced Lithography Technologies: When developing lithography processes for 2Xnm and below design nodes, researchers need to evaluate EUV lithography, double patterning lithography and creative single patterning lithography technologies. They must understand how pattern printing is affected by lithography variables, such as mask sets, stepper parameters and resist materials. The traditional method of evaluating these lithography technologies – printing hundreds of test wafers using experimental materials and prototype process equipment – would be complex, expensive, and time consuming. PROLITH X3.1 acts as a virtual lithography tool, providing researchers with an affordable means for advanced modeling different lithography technologies and reducing the development time for their most advanced devices.

EUV Lithography: The PROLITH X3.1 virtual lithography tool includes advanced stochastic and photoelectron models that quickly and accurately predict pattern printing for EUV lithography. Using PROLITH, researchers have an affordable means to explore EUV lithography and the many variables and issues associated with the technology. One such issue is line edge roughness (LER), which can cause CD uniformity problems that negatively impact device yield and performance. Version X3.1’s advanced models help researchers accurately predict LER and cost-effectively explore potential solutions for minimizing LER.

Wafer Topography: Wafer topography is an important consideration when implementing double patterning processes in the lithography cell. The first-pass resist patterns in DPL contort the imaging materials coated over them, resulting in non-planar resist surfaces for second-pass patterning. The PROLITH X3.1 virtual lithography tool includes enhanced wafer topography models and improved ease-of-use for the set-up of non-planar resist profiles. These enable lithographers to more accurately predict the outcome of DPL processes and allow the simulation of next-generation non-planar devices like FinFETS and other non-planar, real-world wafer stacks (e.g. STI layers, implant layers, damascene structures).
 

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