KLA-Tencor Accelerates Reticle Design Verification For Sub-100-nm Device Production With Design Process Window Qualification Technology
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PWQ methodology provides essential check in design-for-manufacturing chain by identifying reticle design errors such as yield-limiting RET marginalities

SAN JOSE, Calif., May 7, 2003--In a move that could greatly increase the manufacturability of advanced reticle designs, KLA-Tencor (NASDAQ: KLAC) today introduced Process Window Qualification (PWQ), the industry's first solution that enables lithographers to qualify the process window for their sub-100-nm designs prior to production. Combining state-of-the-art wafer inspection and analysis, PWQ identifies reticle design errors, such as marginalities in optical proximity correction (OPC) and other resolution enhancement techniques (RETs), which can cause process window failures and result in catastrophic yield losses. In addition, PWQ can be used to tighten the calibration of the OPC models.

"Extending optical lithography to the 90-nm node and beyond leaves little room for process error," said Dr. Burn Lin, senior director, Micropatterning Technology Division at TSMC, one of several early users of PWQ. "We need to take into account all possible sources that can reduce the size of the process window and impact the manufacturability of the design. PWQ provides an extra measure of certainty that every design is qualified for production. PWQ's ability to identify OPC design and other RET marginalities is useful for qualifying advanced reticle designs at 90 nm and below."

Aggressive optical lithography requires reticle design verification on product
Currently, design rule check (DRC) and optical rule check (ORC) software models are used to verify that the design and RETs are done correctly at the physical design level. Today, running these models for the entire chip design and the entire focus process window can take anywhere from days to weeks, or even months, causing delays in bringing a design to market. As a result, these checks are typically done at best focus and exposure conditions, and only some sections of the chip are checked through the entire process window. This is no longer adequate in today's advanced chip manufacturing environment, where RET complexity, combined with lens aberrations and focus and exposure non-uniformity, can reduce the process window for certain features. Even if a reticle is manufactured to specification and is defect free, features with defective or non-optimized RETs can fall outside the lithography process window and cause significant yield losses. Since these pattern anomalies are not design rule errors or defects on the reticle, they cannot be detected using reticle inspection or design rule check tools.

With the continued delay in the introduction of next-generation lithography, the semiconductor industry has had to adopt increasingly complex RETs in order to extend optical lithography below the 100-nm node. By the 65-nm node, more than 20 layers in a mask set will require aggressive RETs, and every one of these layers will require OPC models that are calibrated to each reticle/scanner/resist combination. Even with the most sophisticated models, however, chip manufacturers will still need to verify the reticle design on product reticles for each tool set. KLA-Tencor's PWQ solution complements design-for-manufacturability software by providing this additional check. In addition to helping to tighten the calibration of OPC models, PWQ enables design errors to be quickly identified and corrected upstream.

PWQ: Unique methodology for more informed and faster decision-making
PWQ uses a specified wafer layout, which is inspected on KLA-Tencor's 23xx series high-resolution imaging inspection system--a tool that provides the highest sensitivity to pattern anomalies. After data has been collected from the 23xx, it is further analyzed via proprietary algorithms to identify and prioritize repeating regions of process window marginality. This enables lithographers to identify at what point marginal design features will print as pattern errors, and, thus, which features are at the greatest risk of falling outside the process window. As a result, lithographers can make more informed decisions about whether to have the reticle re-designed, or instead fine-tune their in-line defect and critical dimension (CD) monitoring efforts to minimize the impact that the design errors can have on device yields.

"As we shrink to smaller technology nodes, the line between defects and parametric performance begins to blur. This holds true especially for lithography, where a small dimensional error can result in an actual defect," stated Rick Wallace, executive vice president of KLA-Tencor's Wafer Inspection, Review and Analysis Group. "While lithography continues to increase in complexity and cost, it also plays a more critical role in a fab's overall production success. This places enormous pressure on lithographers to ensure their processes are stable and manufacturable. Combined with reticle inspection, PWQ offers a highly effective methodology for minimizing the impacts and delays associated with ramping advanced designs into high-volume production."

Several leading semiconductor foundries and integrated device manufacturers (IDMs) have implemented PWQ in their production line.

Note to Editors: A technical fact sheet on PWQ is available upon request.

About KLA-Tencor: KLA-Tencor is the world leader in yield management and process control solutions for semiconductor manufacturing and related industries. Headquartered in San Jose, Calif., with operations around the world, KLA-Tencor ranked #6 on S&P's 2002 index of the top 500 companies in the U.S. KLA-Tencor is traded on the Nasdaq National Market under the symbol KLAC. Additional information about the company is available on the Internet at http://www.kla-tencor.com

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